The present application describes systems and methods relating to information flow and analyzing faults in integrated circuits for digital devices and microprocessor systems.
Integrated circuits are ubiquitous and govern safety-critical systems, including automobiles, medical devices, and aerospace/defense systems. A failure in any one of these systems can potentially result in catastrophic losses, both financially and fatally for users and bystanders alike. Because of this, it is desirable for hardware designers developing these integrated circuits to provide integrated circuits that operate correctly and safely even in the presence of faults, which are defects that can potentially change the intended behavior of the system. However, some existing techniques for analyzing these effects of faults in integrated circuits are both cost-heavy and time-intensive, and eventually produce low-quality results. For example, hardware designers, can currently employ fault analysis techniques that include: 1) manual inspection of the design files, and 2) using fault-simulation platforms, which tend to give fault coverage numbers that may be significantly reduced (e.g., inadequate to meet verification standards for automotive and aeronautical systems). Hardware designers are looking for any solutions that can help them generate better results in less time.